Enhanced Clock Gating Technique for Power Optimization in SRAM and Sequential Circuit


Keywords: Enhanced clock gating, D-Latch gating, SRAM, sequential circuit, Area, Delay


Low power VLSI designs are having wide variety of application usage in real-time. VLSI circuits are analyzed with various power reduction strategies. Existing approaches are used the clock frequency control, switching activity and scaling factor for power reduction. The glitching problem and clock triggering issues are higher therefore; the proposed work utilized the improved circuit of clock gating technique. In this proposed work, the enhanced clock gating with D-latch model is constructed to obtain the less power consumption. The traditional clock gating technique is improved by adding clock triggering on LATCH circuit and adding buffer circuit between the source and load circuitry to reduce the clock switching issues like gitching and clocking activity. Here the SRAM and sequential counter circuits are designed to utilize the power reduction strategy for improving the performance. This is applicable for various applications in real world and utilizing the FPGA and DSP application specific circuits. Experimental results are analyzed to obtain the power reduction result of SRAM and sequential circuit. Area, power, and delay are obtained the better results as compared with the previous work. Overall, design is performed using Xilinx 14.2 ISE suit.

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How to Cite

Enhanced Clock Gating Technique for Power Optimization in SRAM and Sequential Circuit. (2022). Journal of Automation, Mobile Robotics and Intelligent Systems, 15(2), 32-38. https://doi.org/10.14313/JAMRIS/2-2021/11

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