Enhanced Clock Gating Technique for Power Optimization in SRAM and Sequential Circuit


Keywords: Enhanced clock gating, D-Latch gating, SRAM, sequential circuit, Area, Delay


Low power VLSI designs are having wide variety of application usage in real-time. VLSI circuits are analyzed with various power reduction strategies. Existing approaches are used the clock frequency control, switching activity and scaling factor for power reduction. The glitching problem and clock triggering issues are higher therefore; the proposed work utilized the improved circuit of clock gating technique. In this proposed work, the enhanced clock gating with D-latch model is constructed to obtain the less power consumption. The traditional clock gating technique is improved by adding clock triggering on LATCH circuit and adding buffer circuit between the source and load circuitry to reduce the clock switching issues like gitching and clocking activity. Here the SRAM and sequential counter circuits are designed to utilize the power reduction strategy for improving the performance. This is applicable for various applications in real world and utilizing the FPGA and DSP application specific circuits. Experimental results are analyzed to obtain the power reduction result of SRAM and sequential circuit. Area, power, and delay are obtained the better results as compared with the previous work. Overall, design is performed using Xilinx 14.2 ISE suit.

C. Ashok Kumar, B. K. Madhavi and K. Lal Kishore, “Methods and Analysis for Low Power VLSI Design”, The International Journal of Analytical and Experimental Modal Analysis, vol. 12, no. 1, 2020, 3427-3435.

B.-C. C. Lai and J.-L. Lin, “Efficient Designs of Multiported Memory on FPGA”, IEEE Trans. on Very Large Scale Integr. (VLSI) Syst., vol. 25, no. 1, 2017, 139-150, 10.1109/TVLSI.2016.2568579.

X.-T. Nguyen, T.-T. Hoang, H.-T. Nguyen, K. Inoue and C.-K. Pham, “An Efficient I/O Architecture for RAM-Based Content-Addressable Memory on FPGA”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 3, 2019, 472-476, 10.1109/TCSII.2018.2849925.

N. Srinivasan, N. S. Prakash, Shalakha D., Sivaranjani D., S. Sri Lakshmi G. and B. B. T. Sundari, “Power Reduction by Clock Gating Technique”, Procedia Technology, vol. 21, 2015, 631-635, 10.1016/j.protcy.2015.10.075.

J. Shinde and S. S. Salankar, “Clock gating — A power optimizing technique for VLSI circuits”. In: 2011 Annual IEEE India Conference, 2011, 1-4, 10.1109/INDCON.2011.6139440.

J. Monteiro and S. Devadas, “Optimization Techniques for Low Power Circuits”. In: Computer-Aided Design Techniques for Low Power Sequential Logic Circuits, 1997, 81-96, 10.1007/978-1-4615-6319-8_5.

P. Singh and R. Goel, “Clock Gating: A Comprehensive Power Optimization Technique for Sequential Circuits”, International Journal of Advanced Research in Computer Science & Technology, vol. 2, no. 2, 2014, 321-324.

Z. A. Khan, S. M. Aqil Burney, J. Naseem and K. Rizwan, “Optimization of Power Consumption in VLSI Circuit”, International Journal of Computer Science Issues, vol. 8, no. 2, 2011, 648-653.

S. Nireekshan Kumar and J. Grace Jency Gnannamal, “Delay and Power Optimization of Sequential Circuits through DJP Algorithm”. In: Proc. of the World Congress on Engineering, vol. 1, London, U.K, 2008.

J. Monteiro, J. Rinderknecht, S. Devadas and A. Ghosh, “Optimization of combinational and sequential logic circuits for low power using precomputation”. In: Proc. 16th Conference on Advanced Research in VLSI, 1995, 430-444, 10.1109/ARVLSI.1995.515637.

P. Zhao, Z. Wang and G. Hang, “Power optimization for VLSI circuits and systems”. In: 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, 2010, 639-642, 10.1109/ICSICT.2010.5667299.

S.-H. Weng, Y.-M. Kuo and S.-C. Chang, “Timing Optimization in Sequential Circuit by Exploiting Clock-Gating Logic”, ACM Transactions on Design Automation of Electronic Systems, vol. 17, no. 2, 2012, 1-15, 10.1145/2159542.2159548.

P. Sreenivasulu, K. Srinivasa Rao and A. Vinaya Babu, “Optimizing Power in Sequential Circuits by Reducing Leakage Current using Enhanced Multi Threshold CMOS”, Indian Journal of Science and Technology, vol. 9, no. 36, 2016, 10.17485/ijst/2016/v9i36/102601.

A. Jagadeeswaran and C. N. Marimuthu, “Power Optimization Techniques for Sequential Elements Using Pulse Triggered Flip-Flops with SVL Logic”, IOSR Journal of VLSI and Signal Processing, vol. 1, no. 4, 2012, 31-36, 10.9790/4200-0143136.

R. Samanth, C. Chaitanya and G. S. Nayak, “Power Reduction of a Functional unit using RT-Level Clock-Gating and Operand Isolation”. In: 2019 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), 2019, 1-4, 10.1109/DISCOVER47552.2019.9008025.

D. Mahesh Kumar and R. Kannusamy, “An Efficient Design of Low Power Sequential Circuit Using Clocked Pair Shared Flip Flop”, Int. J. Appl. Eng. Res., vol. 12, no. 2, 2017, 233-237.

D. Kumar Sharma, “Effects of Different Clock Gating Techinques on Design”, Int. J. Sci. Eng. Res., vol. 3, no. 5, 2012.

A. Nag and S. N. Pradhan, “An Autonomous Power and Clock Gating Technique in SRAM-Based FPGA”. In: V. Nath (eds.), Proc. of the International Conference on Nano-electronics, Circuits & Communication Systems, vol. 403, 2017, 1-14, 10.1007/978-981-10-2999-8_1.

L. Sterpone, L. Carro, D. Matos, S. Wong and F. Fakhar, “A new reconfigurable clock-gating technique for low power SRAM-based FPGAs”. In: 2011 Design, Automation & Test in Europe, 2011, 1-6, 10.1109/DATE.2011.5763128.

M. Tamilselvi, P. Vedhanayagi and K. Ramasamy, “Implementation of 13T SRAM Using Power Gated Techniques”, International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, vol. 6, no. S1, 2017, 147-156.

M. Janaki Rani, “Leakage Power Reduction and Analysis of CMOS Sequential Circuits”, International Journal of VLSI Design & Communication Systems, vol. 3, no. 1, 2012, 13-23, 10.5121/vlsic.2012.3102.



How to Cite

Ashok Kumar, C., Madhavi, B., & Kishore, K. L. . (2022). Enhanced Clock Gating Technique for Power Optimization in SRAM and Sequential Circuit. Journal of Automation, Mobile Robotics and Intelligent Systems, 15(2), 32-38. https://doi.org/10.14313/JAMRIS/2-2021/11